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[AK4223] ms1251-e-00 1 2010/10 general description the AK4223 is an av switch with 6:2 audio and 6:2 vi deo switches. high perform ances with low power consumption are achieved by cmos process. integrated differ ential input circuits in audio and video blocks can separate the external ground noise. in audi o block, a differential input circuit, audio lpf and 0db/-6db gain amplifier are integrat ed eliminating the needs for exter nal lpf for audio outputs. in video block, an input clamp circuit, 6db amplifier and video driver are integr ated, and they also eliminate the need for external circuits. the AK4223 is offered in a space saving small 48-pin lqfp package, ideal for car navigation applications. features 1. audio section ? selector with 6 inputs and 2 outputs ? differential input circuit for ground noise canceling ? lpf circuit for audio signals ? output gain control: 0db - 6db, -1db step ? s/(n+d): 90db (@0dbv) ? dynamic range: 94db ? channel-independent mute function 2. video section ? selector with 6 inputs and 2 outputs ? six composite signal inputs ? on-chip sync-tip clamp circuit ? video drivers for composite signa l output (+6db/+3db/0db/-3db) ? output gain control: -1db +1db, 0.1db step ? lpf circuit for video signals (bandwidth: 6mhz) ? s/n: 65db ? channel-independent mute function 3. control section ? serial p i/f (i 2 c) 4. power supply: 7.5v 9.5v 5. ta = -40 85 c 6. package: 48pin lqfp 6:2 audio switch and 6:2 video switch AK4223
[AK4223] ms1251-e-00 2 2010/10 vcom input #1 (same circuit) input #2 (same circuit) input #3 (same circuit) input #4 (same circuit) input #5 lin1 gnd1 rin1 lin2 lin3 lin4 lin5 gnd2 gnd3 gnd4 gnd5 rin2 rin3 rin4 rin5 (same circuit) (same circuit) (same circuit) (same circuit) vin1 vgnd1 vin2 vgnd2 vin3 vgnd3 vin4 vgnd4 vin5 vgnd5 sw3 sw4 lpf lpf vout2 vout1 rout2 lout2 rout1 lout1 scl sd a a vdd regv vcom register control audio block video block (same circuit) vin6 vgnd6 0db~ -6db 0db~ -6db 0db~ -6db 0db~ -6db vr2 rstn sw1 sw2 bias bias lpf regulator2 regulator1 vss1 vr1 (same circuit) input #6 lin6 gnd6 rin6 lpf lpf lpf vvdd vss2 ? 3/0/+3/+6db rvdd gca gca figure 1. AK4223 block diagram
[AK4223] ms1251-e-00 3 2010/10 ordering guide AK4223vq -40 a +85 q c 48pin lqfp (0.5mm pitch) akd4223 evaluation board for AK4223 pin layout lin3 37 vcom 36 38 rin2 39 gnd2 40 lin2 41 rin1 42 43 gnd1 44 lin1 45 sda 46 scl 47 gnd3 35 3 4 33 32 31 30 29 28 2 7 26 vin 6 1 vgnd5 2 vin5 3 vgnd4 4 vin4 5 vgnd3 6 vin 3 7 vgnd2 8 vin 2 9 vgnd1 10 vin1 11 23 22 21 20 19 18 17 16 15 14 13 vr1 vout1 vout2 top view vss2 48 vr2 12 24 25 vgnd6 vss1 AK4223 rstn regv a vdd vvdd rout2 rvdd lout2 rout1 lout1 rin4 lin5 gn d5 rin5 lin6 gnd6 rin6 rin3 lin4 gnd4
[AK4223] ms1251-e-00 4 2010/10 pin/function no. pin name i/o function 1 vin6 i video signal input pin 6. 2 vgnd5 i video gnd input pin 5. 3 vin5 i video signal input pin 5. 4 vgnd4 i video gnd input pin 4. 5 vin4 i video signal input pin 4. 6 vgnd3 i video gnd input pin 3. 7 vin3 i video signal input pin 3. 8 vgnd2 i video gnd input pin 2. 9 vin2 i video signal input pin 2. 10 vgnd1 i video gnd input pin 1. 11 vin1 i video signal input pin 1. 12 vr2 o video signal clamp reference pin 2. normally connected to vss2 with a 0.1 f capacitor. 13 vout2 o video signa l output pin 2. 14 vout1 o video signa l output pin 1. 15 vr1 o video signal clamp reference pin 1. normally connected to vss2 with a 0.1 f capacitor. 16 regv o regulator output pin for the power supply of video core circuit. 5.0v (typ) for stability of the regulator, this pi n must connect to vss2 with a 10 p f capacitor. 17 rstn i reset mode pin ?l?: reset mode (all registers are initialized to their default values.) ?h?: normal operation 18 vvdd - power supply pin: 7.5v~9.5v 19 avdd - power supply pin: 7.5v~9.5v 20 rvdd - power supply pin: 7.5v~9.5v 21 rout2 o audio signal output pin rout 2. 22 lout2 o audio signal output pin lout 2. 23 rout1 o audio signal output pin rout 1. 24 lout1 o audio signal output pin lout 1. 25 rin6 i audio signal input pin rin 6. 26 gnd6 i audio gnd input pin gnd 6. 27 lin6 i audio signal input pin lin 6. 28 rin5 i audio signal input pin rin 5. 29 gnd5 i audio gnd input pin gnd 5. 30 lin5 i audio signal input pin lin 5. 31 rin4 i audio signal input pin rin 4. 32 gnd4 i audio gnd input pin gnd 4. 33 lin4 i audio signal input pin lin 4. 34 rin3 i audio signal input pin rin 3. 35 gnd3 i audio gnd input pin gnd 3. 36 lin3 i audio signal input pin lin 3. 37 vss1 - audio ground pin 38 rin2 i audio signal input pin rin 2. 39 gnd2 i audio gnd input pin gnd 2. 40 lin2 i audio signal input pin lin 2.
[AK4223] ms1251-e-00 5 2010/10 pin/function (continued) no. pin name i/o function 41 rin1 i audio signal input pin rin 1. 42 gnd1 i audio gnd input pin gnd 1. 43 lin1 i audio signal input pin lin 1. 44 vcom o audio vcom voltage pin. normally connected to vss1 with a 1 f electrolytic capacitor. 45 sda i/o control data pin. 46 scl i control data clock pin. 47 vss2 - video ground pin. 48 vgnd6 i video gnd input pin 6. v handling of unused pin the unused i/o pins should be processed appropriately as below. classification pin name setting audio inputs lin1-6, rin1-6, gnd1-6 these pins must be open. video input vin1-6, vgnd1-6 these pins must be connected to vss2. audio, video outputs lout 1-2, rout1-2, vout1-2 thes e pins must be open.
[AK4223] ms1251-e-00 6 2010/10 absolute maximum ratings (vss1=vss2 =0v; note 1 ) parameter symbol min max units power supply avdd vvdd rvdd -0.3 +14.0 v input current (any pins except for supplies) iin - 10 ma audio input voltage vina -0.3 avdd+0.3 v video input voltage vinv -0.3 5.5 v digital input voltage vind -0.3 5.5 v ambient operating temperature ta -40 85 c storage temperature tstg -65 150 c note 1. all voltages with respect to ground. note 2. vss1 and vss2 must be connected to the same analog ground plane. note 3. avdd and rvdd must be the same voltage. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guara nteed at these extremes. recommended operating conditions (vss1=vss2 = 0v) parameter symbol min typ max units power supply avdd vvdd rvdd 7.5 9.0 9.5 v note 3. avdd and rvdd must be the same voltage. *akm assumes no responsibility for the usage beyond the conditions in this datasheet. electrical characteristics (ta=25 c; avdd= rvdd= vvdd= 9.0v; vss1= vss2 = 0v) power supplies parameter min typ max units power supply (avdd+rvdd+vvdd) normal operation ( note 4 ), (rstn pin = ?h?) power-down mode ( note 5 ), (rstn pin = ?l?) 33 2.1 50 3.1 ma a note 4. no input, no load. note 5. this is the value without analog inputs when all digital input pins are fixed to vss1 or vss2.
[AK4223] ms1251-e-00 7 2010/10 analog characteristics (audio) (ta=25 c; avdd= rvdd= vvdd= 9.0v; vss1=vss2= 0v; signa l frequency=1khz, measurement frequency= 20hz 20khz, unless otherwise specified) parameter conditions min typ max units s/(n+d) ( note 6 ) input=0dbv 82 90 db dr (0dbv reference) ( note 6 ) input=-60dbv, a-weighted 88 94 db s/n (0dbv reference) ( note 6 ) a-weighted 88 94 db input impedance 70 100 k input voltage ( note 7 ) 2 vrms 0db -0.4 0 +0.4 db gain -6db -6.4 -6.0 -5.6 db agca step ( note 6 ) - 1.0 - db interchannel isolation ( note 8 ) - 100 db response at 24khz -2 -0.5 - db lpf frequency response input=1vrms, 0db at 1khz response at 96khz - -24 - db interchannel gain mismatch 0.2 - db gain drift 20 - ppm/ c load resistance ( note 9) r1 ( figure 2 ) r1+r2 ( figure 2 ) 300 5 k load capacitance c1 ( figure 2 ) c2 ( figure 2 ) 1.5 30 nf pf power supply rejection ( note 10 ) - 74 db cmrr f=1khz, 1vp-p input 35 45 db note 6. this is a value when agca=0db. note 7. the input voltage meets s/(n+d)>82db. note 8. between all channels of lin1-6 and rin1-6. note 9. the output resistance of audio output (lout1-2 and rout1-2) are less than l0 (typ). note 10. applied to avdd, rvdd and vvdd w ith a sine wave (1khz, 50mvpp). lout/rout r1 300 c3 10uf c2=c21+c22= 30pf(max) c1= 1.5nf(max) r2 4.7k c21 c22 c1 figure 2. load resistance r1, r2 and load capacitance c1, c2
[AK4223] ms1251-e-00 8 2010/10 analog characteristics (video) (ta = 25 c; avdd= rvdd= vvdd= 9.0v; vss1= vss2 = 0v; vgain= +6db, vgca=0db; vr 1/2 bit=?0?; unless otherwise specified.) parameter conditions min typ max units vgain=+3db, +6db 200 mv sync tip clamp level ( note 11 ) vgain=-3db, 0db 500 mv 6db - 7 - db 3db - 4 - db 0db - 1 - db vgca=+1db -3db - -2 - db 6db 5.6 6 6.4 db 3db 2.6 3 3.4 db 0db -0.4 0 0.4 db vgca=0db -3db -3.4 -3 -2.6 db 6db - 5 - db 3db - 2 - db 0db - -1 - db gain input=0.3vp-p, 100khz vgca=-1db -3db - -4 - db vgca step - 0.1 - db response at 6mhz -1.0 +1.0 db response at 27mhz - -35 - db frequency response input=0.3vpp, sin wave (0db at 100khz) group delay distortion |gd3mhz ? gd6mhz| 10 40 ns input impedance 300 k input signal 1.5 vpp inter channel isolation f=4.43mhz, 1vpp input - 52 db s/n reference level = 0.7vp-p, bw= 100khz to 6mhz. - 65 db differential gain 0.7vpp 5steps modulated staircase. chrominance & burst are 280mvpp, 4.43mhz. +0.4 - % differential phase 0.7vpp 5steps modulated staircase. chrominance & burst are 280mvpp, 4.43mhz. +1 - degree vr1/2 bit = ?0?, r1+r2 ( figure 4 ) 140 150 160 load resistance vr1/2 bit = ?1?, r1 ( figure 5 ) 100 - - k vr1/2 bit = ?0?, ( figure 4 ) c1 c2 1.5 15 nf pf load capacitance vr1/2 bit = ?1?, ( figure 5 ) c1+c2 15 pf cmrr f=20khz, 1vp-p input 34 55 db note 11. at the measurement point a in figure 3 . idling dc output level is 200mv(max) when vgain=+6db or +3db, and 500mv(max) when vgain=0db or -3db. vout 75 75 0v a pedestal volltage a: 100mv(max): vgain=+3db, +6db measurment point a figure 3. measurement point
[AK4223] ms1251-e-00 9 2010/10 vout 75 75 max:1.5nf (c1) c1 r1 r2 max: 15pf (c2) c2 figure 4. load resistance r1+r2 and load capacitance c1/c2 (vr1/2 bit = ?0?) vout c1 r1 c1+c2=15pf (max) c2 c 100k (m i n) figure 5. load resistance r1+r2 and load capacitance c1/c2 (vr1/2 bit = ?1?) dc characteristics (ta=-40~85 c; avdd= rvdd= vvdd= 7.5 9.5v) parameter symbol min typ max units high-level input voltage (rstn,scl,sda,cad pins) low-level input voltage (rstn,scl,sda,cad pins) vih vil 2.7 - - - 5.5 0.8 v v low-level output voltage (sda pin: iout=3ma) vol - - 0.4 v input leakage current iin - - 10 a switching characteristics (ta= 25 c; avdd =rvdd= vvdd= 9.0v) control interface timing (i 2 c bus) scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 13 ) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 - 400 - - - - - - - 0.3 0.3 - 50 400 khz s s s s s s s s s s ns pf power-down & reset timing rstn reject pulse width rstn pulse width ( note 14 ) trpd tpd 150 15 ns ns note 12. i 2 c-bus is a trademark of nxp b.v. note 13. data must be held long enough to bridge the 300ns-transition time of scl. note 14. the AK4223 can be reset by setting the rstn pin = ?l? when powered up.
[AK4223] ms1251-e-00 10 2010/10 timing diagram thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp figure 6. i 2 c bus mode timing tpd rstn vil figure 7. reset mode timing
[AK4223] ms1251-e-00 11 2010/10 operation overview power up/down the AK4223 can be reset by bringing the rs tn pin = ?l? upon power-up. in reset m ode, internal resisters are initialized and the audio and video circuits are in power-down state out putting hi-z signals. the rstn pin must be ?l? to execute this reset when power up the AK4223. audio and video signal inputs 1. audio signal input the ground noise is cancelled by the differential input with the same ground for l and r channels. the output of lin and rin are the same phase. lin1-6, rin1-6 and gnd1-6 pi ns must be ac coupled with a 0.47uf capacitor. lin1-6 rin1-6 0.47 f (cable) 0.47 f gnd1-6 (cable) figure 8. audio input circuit (differential) lin1-6 rin1-6 0.47 f (cable) 0.47 f gnd1-6 figure 9. audio input circuit (single-ended) 2. video signal input sync-tip output level is fixed by the internal clamp circuit. vin1-6 pins must be input via a 0.1uf capacitor for ac coupling. vin1-6 0.1 f (cable) 0.1 f vgnd1-6 (cable) figure 10. video input circuit (differential) vin1-6 0.1 f (cable) 0.1 f vgnd1-6 figure 11. video input circuit (single-ended)
[AK4223] ms1251-e-00 12 2010/10 input selector the AK4223 has 6:2 input selectors for audio input, and 6:2 input selectors for video input. the audio input selectors are set by asel12-10bits and asel22-20 bits, and the video input selectors are set by vsel12-10bits and vsel22-20 bits. asel12 bit asel11 bit asel10 bit input selector 0 0 0 off ( note 15 ) (default) 0 0 1 lin1 / rin1 0 1 0 lin2 / rin2 0 1 1 lin3 / rin3 1 0 0 lin4 / rin4 1 0 1 lin5 / rin5 1 1 0 lin6 / rin6 1 1 1 (reserved) table 1. audio input selector 1 (lout1/rout1) asel22 bit asel21 bit asel20 bit input selector 0 0 0 off ( note 15 ) (default) 0 0 1 lin1 / rin1 0 1 0 lin2 / rin2 0 1 1 lin3 / rin3 1 0 0 lin4 / rin4 1 0 1 lin5 / rin5 1 1 0 lin6 / rin6 1 1 1 (reserved) table 2. audio input selector 2 (lout2/rout2) note 15. the audio outputs become 3.9v(typ., gain=0db) when input selectors are off. vsel12 bit vsel11 bit vsel10 bit input selector 0 0 0 off ( note 16 ) (default) 0 0 1 vin1 0 1 0 vin2 0 1 1 vin3 1 0 0 vin4 1 0 1 vin5 1 1 0 vin6 1 1 1 (reserved) table 3. video input selector 1 (vout1) vsel22 bit vsel21 bit vsel20 bit input selector 0 0 0 off ( note 16 ) (default) 0 0 1 vin1 0 1 0 vin2 0 1 1 vin3 1 0 0 vin4 1 0 1 vin5 1 1 0 vin6 1 1 1 (reserved) table 4. video input selector 2 (vout2) note 16. the video outputs become sync tip level when input selectors are off.
[AK4223] ms1251-e-00 13 2010/10 audio output level setting agca12-10 bits control the audio output level of the l/r out1 pin, and agca22-20 bits controls the audio output level of the l/rout2 pin. ( table 5 , table 6 ) agca12 bit agca11 bit agca10 bit l/rout1 gai n [db] output dc level[v typ] step 0 0 0 0 (default) 3.9 0 0 1 -1 3.7 0 1 0 -2 3.5 0 1 1 -3 3.4 1db 1 0 0 -4 3.2 1 0 1 -5 3.1 1 1 0 -6 3.0 1 1 1 reserved - table 5. l/rout1 output level setting agca22 bit agca21 bit agca20 bit l/rout2 gai n [db] output dc level[v typ] step 0 0 0 0 (default) 3.9 0 0 1 -1 3.7 0 1 0 -2 3.5 0 1 1 -3 3.4 1db 1 0 0 -4 3.2 1 0 1 -5 3.1 1 1 0 -6 3.0 1 1 1 reserved - table 6. l/rout2 output level setting audio output mute select the AK4223 has a channel independent mute function for audio outputs. amute1/2 bits control l/rout1 and l/rout2 outputs mute. ( table 7 , table 8 ) amute1 bit l/rout1 output 0 normal output (default) 1 mute table 7. l/rout1 output mute control amute2 bit l/rout2 output 0 normal output (default) 1 mute table 8. l/rout2 output mute control
[AK4223] ms1251-e-00 14 2010/10 video output level setting vgain11-10 bits control the video output level of the vout1 pin, and vgain21-20 bits control the video output level of the vout2 pin. ( table 9 , table 10 ) vgain11 bit vgain10 bit vout1 output le vel vout1 sync tip level (max) 0 0 +6db 200mv (default) 0 1 0db 500mv 1 0 +3db 200mv 1 1 -3db 500mv table 9.vout1 output level setting vgain21 bit vgain20 bit vout2 output le vel vout2 sync tip level (max) 0 0 +6db 200mv (default) 0 1 0db 500mv 1 0 +3db 200mv 1 1 -3db 500mv table 10.vout2 output level setting vgca14-10 bits finely tune the video output levels of vout1, a nd vgca24-20 bits tune vout2. ( table 11 , table 12 ) vgca14-10 bit vout1 gain [db] step 00000 1.0 00001 0.9 00010 0.8 : : 01010 0 (default) 0.1db : : 10010 +0.8 10011 +0.9 10100 +1.0 others reserved table 11. video output leve l (vout1) fine tuning setting vgca24-20 bit vout2 gain [db] step 00000 1.0 00001 0.9 00010 0.8 : : 01010 0 (default) 0.1db : : 10010 +0.8 10011 +0.9 10100 +1.0 others reserved table 12. video output leve l (vout2) fine tuning setting
[AK4223] ms1251-e-00 15 2010/10 video output driver vr1 and vr2 bits control the video output driver of the vout1 and vout2 pins respectivel y. vr1 and vr2 bits should be set to ?0? when driving 150 ? resistance. vr1 bit vout1 0 150 ? drive (default) 1 min. 100k ? drive table 13. vout1 output driver setting vr2 bit vout2 0 150 ? drive (default) 1 min. 100k ? drive table 14. vout2 output driver setting video output mute setting the AK4223 has a channel independent mute function of the video output. vmute1 and vmute2 bits mute (sync tip clamp level) vout1 and vout 2 outputs respectively. ( table 15 , table 16 ) vmute1 bit vout1 output 0 normal output (default) 1 mute table 15. vout1 output mute control vmute2 bit vout2 output 0 normal output (default) 1 mute table 16. vout2 output mute control
[AK4223] ms1251-e-00 16 2010/10 system reset the rstn pin must be set to ?l? when power up the AK4223. the AK4223 powers up in reset state. the regv pin starts outputting (typ. 5.0v) when power is supplied to the device. this reset is released by setting the rstn pin to ?h?. figure 12 shows the reset sequence. power supply (vvdd, avdd, rvdd) vss rstn pin regv pin output (1) regv=5.0v(typ) (2) a udio ? video circuit power down audio output: hi-z power up (3) notes: (1) time that the regv output reaches 95% of the maximum value. (typ. 800 p s, max. 5ms) (2) reset time (min. 150ns) (3) time to be in a normal operation after reset release. (video output: typ. 100ms, audio output: typ. 170ms) *the required time to be in a normal ope ration of audio outputs is proportional to the capacity of an external capacitor at the vcom pin. this typical value 170ms is for when the external capacitor is 1.0 p f. figure 12 system reset diagram
[AK4223] ms1251-e-00 17 2010/10 control interface the AK4223 supports the fast-mode i 2 c-bus system (max: 400khz). 2-1. write operation figure 13 shows the data transfer sequence for the i 2 c-bus mode. all commands are pr eceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition ( figure 19 ). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit that is a data direction bit (r/w). the most significant seven bits of the slave address are fixed as ?0010000?. if the slave address matches that of the AK4223, the AK4223 generates an acknowledge and the opera tion is executed. the master must generate the acknowledge-related clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 20 ). a r/w bit value of ?1? indicates that the r ead operation is to be executed. a ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the AK4223. the format is msb first, and those most significant 3-bits are fixed to zeros ( figure 15 ). the data after the second byte contains control data. the format is msb first, 8bits ( figure 16 ). the AK4223 generates an acknowledge after each by te has been received. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition ( figure 19 ). the AK4223 can perform more than one by te write operation per sequence. after receipt of the third byte the AK4223 generates an acknowledge and awaits the next data. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after r eceiving each data packet the inte rnal 8-bit address counter is incremented by one, and the next data is automatically taken into the next addr ess. if the address exceeds 06h prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. the high or low state of the data line can only change when the cloc k signal on the scl line is low ( figure 21 ) except for the start and stop conditions. sda slave address s s t a r t r/w = "0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 13. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 0 0 r/w figure 14. the first byte 0 0 0 0 0 a2 a1 a0 figure 15. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 16. byte structure after the second byte
[AK4223] ms1251-e-00 18 2010/10 2-2. read operations set the r/w bit = ?1? for the read operation of the AK4223. after transmission of data, the master can read the next address?s data by generating an acknowledge instead of terminating the write cy cle after the receipt of the first data word. after receiving each data packet the inte rnal 5-bit address counter is increm ented by one, and the next data is automatically taken into the next address. if the address exceeds 06h prior to generating a stop condition, the address counter will ?roll over? to 00h and th e previous data will be overwritten. the AK4223 supports two basic read operations: current address read and random address read. 2-2-1. current address read the AK4223 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) were to address ?n ?, the next current read operation would access data from the address ?n+1?. after receipt of the slave address with r/w bit set to ?1?, the AK4223 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4223 ceases transmission. sda slave address s s t a r t r/w = "1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) a c k p s t o p data(n) figure 17. current address read 2-2-2. random address read the random read operation allows the master to access any memo ry location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues a start request, a slave address (r/w bit = ?0?) and then the register address to read. after the register address is acknowledged, the master immediately reissues the start request and the slave address with the r/w bit set to ?1?. the AK4223 then generates an acknowledge, 1 byte of data and increments the internal a ddress counter by 1. if the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4223 ceases transmission. sda slave address s s t a r t r/w = "0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w = "1" s t a r t data(n+1) a c k a c k figure 18. random address read
[AK4223] ms1251-e-00 19 2010/10 scl sda stop condition start condition s p figure 19. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 20. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 21. bit transfer on the i 2 c-bus
[AK4223] ms1251-e-00 20 2010/10 register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 0 0 vmute2 vmute1 0 0 amute2 amute1 01h input selector control1 0 asel 22 asel21 asel20 0 asel12 asel11 asel10 02h input selector control2 0 vsel 22 vsel21 vsel20 0 vsel12 vsel11 vsel10 03h output level control1 0 agca22 agca21 agca20 0 agca12 agca11 agca10 04h output level control2 0 vr2 vr1 0 vgain21 vgain20 vgain11 vgain10 05h output level control3 0 0 0 vgca14 vgca13 vgca12 vgca11 vgca10 06h output level control4 0 0 0 vgca24 vgca23 vgca22 vgca21 vgca20 note: do not write any data to the register over 07h. when the pdn pin changes to ?l?, the registers are initialized to their default values. the bits defined as 0 must contain a ?0? value.
[AK4223] ms1251-e-00 21 2010/10 register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 0 0 vmute2 vmute1 0 0 amute2 amute1 default 0 0 0 0 0 0 0 0 amute2-1: audio output mute control ( table 7 , table 8 ) 0: normal operation (default) 1: mute vmute2-1: video output mute control ( table 15 , table 16 ) 0: normal operation (default) 1: mute addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h input selector control1 0 asel2 2 asel21 asel20 0 asel12 asel11 asel10 default 0 0 0 0 0 0 0 0 asel12-10: audio input selector 1 control ( table 1 ) the lout1/rout2 pin outputs 3.9v (typ., ga in=0db) at the default setting ?000?. asel22-20: audio input selector 2 control ( table 2 ) the lout2/rout2 pin outputs 3.9v (typ., ga in=0db) at the default setting ?000?. addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h input selector control2 0 vsel2 2 vsel21 vsel20 0 vsel12 vsel11 vsel10 default 0 0 0 0 0 0 0 0 vsel12-10: video input selector 1 control ( table 3 ) the video output is sync tip clamp level at the default setting ?000?. vsel22-20: video input selector 2 control ( table 4 ) the video output is sync tip clamp level at the default setting ?000?. addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h output level control1 0 agca22 agca21 agca20 0 agca12 agca11 agca10 default 0 0 0 0 0 0 0 0 agca11-10: audio output l/rout1 level control ( table 5 ) 000: 0db (default) 001: -1db 010: -2db ? 110: -6db 111: reserved agca21-20: audio output l/rout2 level control ( table 6 ) 000: 0db (default) 001: -1db 010: -2db ? 110: -6db 111: reserved
[AK4223] ms1251-e-00 22 2010/10 addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h output level control2 0 vr2 vr1 0 vgain21 vgain20 vgain11 vgain10 default 0 0 0 0 0 0 0 0 vgain11-10: video out put1 level control ( table 9 ) 00: +6db (default) 01: 0db 10: +3db 11: -3db vgain21-20: video out put2 level control ( table 10 ) 00: +6db (default) 01: 0db 10: +3db 11: -3db vr1: video output1 load resistance 0: drive 150 ? (default) 1: drive 100k ? (min) vr2: video output2 load resistance 0: drive 150 ? (default) 1: drive 100k ? (min) addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h output level control3 0 0 0 vgca14 vgca13 vgca12 vgca11 vgca10 default 0 0 0 0 1 0 1 0 vgca14-10: video output1 level control ( table 11 ) the video output is +6db (when vgain11-10 bits = ?00?), 0db (when vgain11-10 bits = ?01?), +3db (when vgain11-10 bits= ?10?) and -3db (when vgain 11-10 bits = ?11?) at the default setting ?01010?. addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h output level control4 0 0 0 vgca24 vgca23 vgca22 vgca21 vgca20 default 0 0 0 0 1 0 1 0 vgca24-20: video output2 level control ( table 12 ) the video output is +6db (when vgain21-20 bits = ?00?), 0db (when vgain21-20 bits = ?01?), +3db (when vgain21-20 bits= ?10?) and -3db (when vgain 21-20 bits = ?11?) at the default setting ?01010?.
[AK4223] ms1251-e-00 23 2010/10 system design figure 22 shows a system connection diagram. an evaluation board [akd4223] is available which demonstrates the optimum layout, power supply arrangements and measurement results. micro controller vin6 1 vgnd5 2 vin5 3 vgnd4 4 vin4 5 vgnd3 6 vin3 7 vgnd2 8 vin2 9 vgnd1 10 vin1 11 vr2 12 13 vout2 14 vout1 lin3 36 gnd3 35 rin3 34 lin4 33 gnd4 32 rin4 31 lin5 30 gnd5 29 rin5 28 lin6 27 gnd6 26 rin6 25 vr1 15 regv 16 rstn 17 vvdd 18 a vdd 19 rvdd 20 rout2 21 lout2 22 rout1 23 lout1 24 audio in a nalog 9v a nalog ground digital ground audio in video out audio out 48 vgnd6 47 vss2 46 scl 45 sd a 44 vcom 43 lin1 42 gnd1 41 rin1 40 lin2 39 gnd2 38 rin2 37 vss1 0.47u video in 0.47u 0.47u 0.47u 0.47u 0.47u 0.47u 0.47u 0.47u 0.47u 0.47u 0.47u 0.47u 0.47u 0 .47u 0.47u 0.47u 0 .47u 1u 10u 10u 10u 10u 300 300 300 300 0.1u 75 0.1u 75 75 75 75 75 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 10u 0.1u 75 75 10u 0.1u 10u vss2 vss1 figure 22. typical connection diagram
[AK4223] ms1251-e-00 24 2010/10 1. grounding and power supply decoupling the AK4223 requires careful attention to power s upply and grounding arrangements. avdd, vvdd and rvdd are usually supplied from the analog power supply in the system. alternatively if avdd, vvdd and rvdd are supplied separately, avdd and rvdd must be pow ered-up at the same time. the power up sequence between avdd/rvdd and vvdd is not critical. vss1 and vss2 must be connected to the analog ground pl ane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as close to the power supply pin of AK4223 as possible. 2. voltage reference vcom is a signal ground of this chip. an 1 f electrolytic capacitor attached betw een vcom and vss1 eliminates the effects of high frequency noise. no load current may be draw n from the vcom pin. to avoid coupling to the AK4223, all signals and especially clock signals should be kept away as far as possible from the vcom pin. 3. notes for drawing a board analog input and output pins should be as short as possibl e in order to avoid unwanted coupling into the AK4223. the unused pins should be open.
[AK4223] ms1251-e-00 25 2010/10 package 1 12 48 13 7.0 9.0 0.2 7.0 9.0 0.2 0.22 0.08 48pin lqfp (unit: mm) 0.10 37 24 25 36 0.09 0.20 1.40 0.05 0.13 0.13 1.70max 0 10 0.10 m 0.3 0.75 0.5 v package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatmen t: solder (pb free) plate rohs compliance *all integrated circuits form asahi kasei micr odevices corporation (akm ) assembled in ?lead-free? packages are fully co mpliant with rohs.
[AK4223] ms1251-e-00 26 2010/10 marking a k4223vq xxxxxxx 1 xxxxxxxx: date code identifier date (yy/mm/dd) revision reason page contents 10/10/22 00 first edition revision history
[AK4223] ms1251-e-00 27 2010/10 important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application exampl es of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your e quipments. akm assumes no responsibility fo r any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the applica tion or use of such information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility fo r such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products , who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above conten t and conditions, and the buyer or distributor agrees to assume any and all responsib ility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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